1. Field of the Invention
The present invention relates to techniques for communicating signals in semiconductor dies and multi-chip systems. More specifically, the present invention relates to a multi-chip system which includes semiconductor dies that communicate signals using on-chip photonics.
2. Related Art
Advances in semiconductor technology have led to significant increases in the performance of integrated circuits, such as microprocessors. For example, the clock frequency of microprocessors has increased from 16 MHz in 1985 to 3600 MHz by 2005, an improvement of 230 times, which represents an annual growth rate of nearly 30%. This performance trend has allowed computers to perform increasingly complicated functions across a wide variety of applications.
Unfortunately, several issues are beginning to constrain further increases in the clock frequency. In particular, the latency of global on-chip wires increases as technology scaling reduces their thickness but not their length. In contrast, many local wires do not suffer from this delay penalty because their lengths shrink along with their thickness.
Moreover, as integration densities and clock frequencies continue to increase, the power consumption of high-performance microprocessors also increases. Consequently, many existing microprocessors consume over 100 W of power, which strains the capabilities of air cooling systems. In fact, many microprocessors have become power-limited, which means they could be operated at higher clock frequencies at the cost of significant increases in power consumption, and thus, in required cooling.
These design constraints have led designers to change the architecture of modern microprocessors. In particular, many microprocessors now include multiple processor cores. These processor cores keep computation and associated communication operations local, which reduces global delays in critical paths. Additionally, individual processor cores can be selectively enabled, thereby allowing unused processor cores to be put into a sleep mode to conserve power and then awakened when they are needed. Moreover, the use of smaller processor cores with shared logical blocks reduces the cost of developing and debugging microprocessors.
Furthermore, many multiple-core microprocessors support chip multi-threading (CMT). This technique helps address the increasing gap between microprocessor performance and the latency associated with fetching instructions and data from main memory, which has grown from a few clock cycles to hundreds of clock cycles over the past two decades. This gap often limits system performance because the microprocessor spends an increasing amount of time waiting for memory accesses instead of executing code. In a microprocessor that uses CMT, a thread can be quickly swapped in and out of execution. This rapid thread switching improves overall system throughput because instead of waiting for a memory request to return when the current thread accesses memory, the microprocessor can put the current thread to sleep and reactivate another thread. Consequently, utilization and throughput in such multi-threaded microprocessors is much higher than in single-threaded microprocessors.
However, microprocessors that include multiple cores and support multiple threads executing on each core have higher communication requirements than single-core, single-threaded microprocessors. In particular, these microprocessors use high-bandwidth communication to: maintain coherence; pass messages; and/or perform simultaneous memory accesses. Moreover, as microprocessor throughput continues to increase, corresponding bandwidth requirements are expected to increase to terabits-per-second and beyond. Given the aforementioned latency problems, it may be difficult to meet these requirements using wires.
Hence, what is needed is a method and an apparatus which provide improved intra-chip and inter-chip communication without the problems listed above.